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參數(shù)資料
| 型號(hào)： | M54HC237F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low-Power Mono ADC / Stereo DAC with 6 audio inputs and HP/Speaker Amplifier 48-VQFN -40 to 85 |
| 中文描述： | 3至8線譯碼器鎖存 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 256K |
| 代理商： | M54HC237F1R |
M54HC237
M74HC237
October 1992
3 TO 8 LINE DECODER LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC237F1R
M74HC237B1R
M74HC237M1R
M74HC237C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
.
HIGH SPEED
t
PD
= 12 ns(TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS237
The M54/74HC237 is a high speed CMOS 3 TO 8
LINE DECODER LATCH fabricated in silicon gate
C
2
MOStechnology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
WhenGL goes from low to high, the address present
at the select inputs (A, B, C) is stored in thelatches.
As long as GL remains high no address changes will
be recognized. Output enable controls, G1 and G2
control the state of the outputs independantly of the
selector latch-enable inputs.All oftheoutputs arelow
unlessG1ishigh andG2islow.The ’HC237isideally
suited for the implementation of glitch-free decoders
in stored-address applications in bus oriented sys-
tems. All inputs are equipped with protection circuits
againststaticdischarge and transient excessvoltage.
DESCRIPTION
1/11
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|---|---|
| M54HC237K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD 3 TO 8 LINE DECODER LATCH |
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