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參數(shù)資料
| 型號： | M54HC126F1R |
| 廠商： | 意法半導體 |
| 英文描述： | XTAL MTL SMT HC49/USM |
| 中文描述： | 四總線緩沖器的三態(tài) |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 117K |
| 代理商： | M54HC126F1R |
1/9
March 2004
I
HIGH SPEED:
t
PD
= 8ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 125
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9401-039
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The M54HC125 is an high speed CMOS QUAD
BUFFER (3-STATE) fabricated with silicon gate
C
2
MOS technology.
The device requires the 3-STATE control input G
to be set high to place the output into the high
impedance state.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC125
RAD-HARD QUAD BUS BUFFER (3-STATE)
PIN CONNECTION
ORDER CODES
PACKAGE
FM
EM
DILC
FPC
M54HC125D
M54HC125K
M54HC125D1
M54HC125K1
DILC-14
FPC-14
相關PDF資料 |
PDF描述 |
|---|---|
| M54HC131F1R | 3 TO 8 LINE DECODER/LATCH |
| M54HC131 | 3 TO 8 LINE DECODER/LATCH |
| M54HC132 | QUAD 2-INPUT SCHMITT NAND GATE |
| M54HC132F1R | QUAD 2-INPUT SCHMITT NAND GATE |
| M54HC133 | 13 INPUT NAND GATE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M54HC126M1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD BUS BUFFERS 3-STATE |
| M54HC131 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3 TO 8 LINE DECODER/LATCH |
| M54HC131F1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3 TO 8 LINE DECODER/LATCH |
| M54HC132 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD 2-INPUT SCHMITT NAND GATE |
| M54HC132_04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD QUAD 2-INPUT SCHMITT NAND GATE |
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