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參數(shù)資料
| 型號： | M54HC113F1R |
| 廠商： | 意法半導體 |
| 英文描述： | DUAL J-K FLIP FLOP WITH PRESET |
| 中文描述： | 雙JK觸發(fā)器預置亂竄 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 247K |
| 代理商： | M54HC113F1R |
M54HC113
M74HC113
October 1992
DUAL J-K FLIP FLOP WITH PRESET
B1R
(Plastic Package)
ORDER CODES :
M54HC113F1R
M74HC113B1R
M74HC113M1R
M74HC113C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
f
MAX
= 71 MHz (TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 2
μ
Aat T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS113
The M54/74HC113 is a highspeed CMOSDUAL J-
K FLIP FLOP WITH PRESET fabricated in silicon
gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOSlowpower consumption.Thiscircuitoffersin-
dividual J, K, set,and clockinputs. Thesemonolithic
dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may
be allowed to change when theclock pulse is HIGH
and the bistable will function as shown in the truth
table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on
thenegative-going edgeoftheclock pulse.Allinputs
are equipped with protection circuits against static
discharge and transient excess voltage.
DESCRIPTION
1/11
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| M54HC11D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD TRIPLE 3-INPUT AND GATE |
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| M54HC11K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD TRIPLE 3-INPUT AND GATE |
| M54HC11K1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAD-HARD TRIPLE 3-INPUT AND GATE |
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