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參數(shù)資料
| 型號(hào)： | M54992FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER |
| 中文描述： | 雙CMOS 24位串行輸入鎖存驅(qū)動(dòng) |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 142K |
| 代理商： | M54992FP |
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
M54992P/FP
MITSUBISHI <CONTROL / DRIVER IC>
Symbol
Ratings
Unit
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS
(Ta=-10 to 75
°
C, unless otherwise noted)
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
S-OUT
O
1
– O
24
: OFF
M54992FP
Ta=25
°
C
Mounted on a board
-0.5 – 8
-0.5 – V
CC
+0.5
-0.5 – V
CC
+0.5
-0.5 – 30
120
2.0
1.9
-10 – 75
-55 – 125
V
V
V
V
mA
W
W
°
C
°
C
Limits
Typ.
5
Min.
4
Max.
6
30
Symbol
Test conditions
Unit
Parameter
RECOMMENDED OPERATING CONDITION
(Ta=-10 to 75
°
C, unless otherwise noted)
V
CC
V
O
I
O
Supply voltage
Output apply voltage
Output current (per circuit)
O
1
– O
24
: OFF
O
1
– O
24
: ON
Duty cycle : 50% or below
100
V
V
mA
Limits
Typ.
Min.
0.7V
CC
0
—
—
4.9
—
-100
400
—
—
—
Max.
V
CC
0.3V
CC
25
-25
—
0.1
—
—
0.55
0.4
50
Symbol
Test conditions
Unit
Parameter
ELECTRICAL CHARACTERISTICS
(Ta=25
°
C, V
CC
=5V, unless otherwise noted)
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
V
OL1
V
OL2
I
OLK
I
CC1
I
CC2
V
T+
V
T-
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
Low-level output voltage
Output leak current
Supply current
Misoperation prevention supply voltage.
Ta=-10 – 75
°
C, V
CC
=4 – 6V
V
IH
=5V
V
IL
=0V
|I
O
|
≤
1
μ
A
V
OH
=4.5V
V
OL
=0.4V
I
OL
=100mA
I
OL
=80mA
V
O
=30V(output: OFF)
Input: open
All driver outputs are OFF.
One driver output is ON.
M54992FP (S-OUT)
—
—
2.9
2.6
3.5
3.4
3.1
1
5.0
3.9
3.6
V
V
μ
A
μ
A
V
V
μ
A
μ
A
V
V
μ
A
mA
mA
V
V
Limits
Typ.
Min.
Max.
4
Symbol
Test conditions
Unit
Parameter
TIMING REQUIREMENTS
(Ta=-10 to 75
°
C, unless otherwise noted)
f
(T)
t
w(T)
t
w(L)
t
su
t
h
t
d(T-L)
t
r(T)
t
f(T)
Clock frequency
Clock pulse width
Latch pulse width
Data setup time
Data hold time
Clock-latch time
Clock pulse rise time
Clock pulse fall time
Input duty cycle: 45 – 55%
100
100
50
20
400
500
500
MHz
ns
ns
ns
ns
ns
ns
ns
M54992P
M54992FP
T, S-IN
EN, LATCH
O
1
– O
24
O
1
– O
24
O
1
– O
24
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