
35 OUTPUT BUFFERS
1
18
19
20
24
V
DD
35 LATCHES
35-BIT SHIFT REGISTER
21
22
23
RESET
LOAD
SERIAL
DATA
CLOCK
DATA ENABLE (M5450)
OUTPUT35 (M5451)
BRIGTHNESS
CONTROL
OUTPUT
BIT 34
OUTPUT
BIT 1
100k
5
BLOCK DIAGRAM
(Figure 1)
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
I
V
O(off)
I
O
P
tot
Parameter
Value
– 0.3 to 15
– 0.3 to 15
15
40
1
560
150
– 25 to 85
– 65 to 150
Unit
V
V
V
mA
W
mW
°
C
°
C
°
C
Supply Voltage
Input Voltage
Off State Output Voltage
Output Sink Current
Total Package Power Dissipation at 25
°
C
at 85
°
C
Junction Temperature
Operating Temperature Range
Storage Temperature Range
T
j
T
op
T
stg
5
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
FUNCTIONAL DESCRIPTION
Both the M5450 and the M5451 are specially desi-
gned to operate 4 or 5-digit alphanumeric displays
with minimal interface with the display and the data
source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals,
serial data and clock. Using a format of a leading
"1" followed by the 35 data bits allows data transfer
without an additional load signal. The 35 data bits
are latched after the 36th bit is complete, thus
providing non-multiplexed, direct drive to the dis-
play.
Outputs change only if the serial data bits differ
from the previous time.
Display brightness is determined by control of the
output current LED displays.
A 1nF capacitor should be connected to brightness
control, pin 19, to prevent possible oscillations.
A block diagram is shown in figure 1. For the M5450
a DATA ENABLE is used instead of the 35th output.
The DATA ENABLE input is a metal option for the
M5450.
The output current is typically 20 times greater than
the current into pin 19, which is set by an external
variable resistor. There is an internal limiting resis-
tor of 400
nominal value.
Figure 2 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
M5450 - M5451
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