參數(shù)資料
型號: M52S32162A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 100萬x 16Bit的X 2Banks同步DRAM
文件頁數(shù): 10/30頁
文件大?。?/td> 787K
代理商: M52S32162A
ES MT
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
M52S32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
1.2
10/30
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence (decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
000
001
010
011
100
101
110
111
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
相關(guān)PDF資料
PDF描述
M52S32162A-10BG 1M x 16Bit x 2Banks Synchronous DRAM
M52S32162A-10TG 1M x 16Bit x 2Banks Synchronous DRAM
M52S32162A-7.5BG 1M x 16Bit x 2Banks Synchronous DRAM
M52S32162A-7.5TG 1M x 16Bit x 2Banks Synchronous DRAM
M538002 524,288-Word x 16-Bit or 1,048,576 x 8-Bit Mask ROM
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