- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377830 > M52S16161A-8TG (ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC) 512K x 16Bit x 2Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | M52S16161A-8TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50 |
| 封裝： | 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 770K |
| 代理商： | M52S16161A-8TG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
ES MT
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
M52S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.5
9/29
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence (decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
000
001
010
011
100
101
110
111
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52S32162A | 1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-10BG | 1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-10TG | 1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-7.5BG | 1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-7.5TG | 1M x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52S32162A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A_08 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Mobile Synchronous DRAM |
| M52S32162A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-10BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM |
| M52S32162A-10BIG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 32MB 2.5V 100MHZ FBGA54 |
發(fā)布緊急采購，3分鐘左右您將得到回復。