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參數(shù)資料
| 型號： | M52D32321A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 512K x 32Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 32Bit的x 2Banks同步DRAM |
| 文件頁數(shù)： | 3/29頁 |
| 文件大?。?/td> | 707K |
| 代理商： | M52D32321A |
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ES MT
FUNCTIONAL BLOCK DIAGRAM
M52D32321A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.3
3/29
Bank Select
Data Input Register
Column Decoder
Latency & Burst Length
Programming Register
512K x 32
512K x 32
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LDQM
LWCBR
DQi
LDQM
LWE
LRAS
LCBR
LWE
LCAS
CLK
ADD
LCKE
PIN FUNCTION DESCRIPTION
Pin
CLK
System Clock
Name
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
CS
Chip Select
CKE
Clock Enable
A0 ~ A10
Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input / Output Mask
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52D32321A-10BG | 512K x 32Bit x 2Banks Synchronous DRAM |
| M52D32321A-7.5BG | 512K x 32Bit x 2Banks Synchronous DRAM |
| M52S128168A | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-10BG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-10TG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52D32321A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32Bit x 2Banks Mobile Synchronous DRAM |
| M52D32321A-10BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32Bit x 2Banks Mobile Synchronous DRAM |
| M52D32321A-7.5BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32Bit x 2Banks Synchronous DRAM |
| M52D32321A-7.5BIG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 32MB 1.8V 166MHZ VFBGA90 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM, 32MB, 1.8V, 166MHZ, VFBGA90 |
| M52D32321A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32Bit x 2Banks Mobile Synchronous DRAM |
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