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參數(shù)資料
| 型號： | M50LPW080N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 8兆1兆× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M50LPW080N |
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M50LPW080
12/44
used. Any other voltage input to V
PP
will result in
undefined behavior and should not be used.
V
PP
should not be set to V
PPH
for more than 80
hours during the life of the memory.
V
SS
Ground.
V
SS
is the reference for all the volt-
age measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual in-
terface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Ad-
dress Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus Op-
erations below and the section Address/Address
Multiplexed (A/A Mux) Interface Bus Operations
below for a description of the bus operations on
each interface.
Low Pin Count (LPC) Bus Operations
The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition protec-
tion against accidental or malicious data corrup-
tion can be achieved using two further signals
(TBL and WP). Finally two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data signals, control signal and clock are de-
signed to be compatible with PCI electrical specifi-
cations. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read.
Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, V
IL
, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed fol-
lowed by Data0-Data3 and Data4-Data7.
See
Table 7.
and
Figure 6.
for a description of the
Field definitions for each clock cycle of the trans-
fer. See
Table 23.
and
Figure 11.
for details on the
timings of the signals.
Bus Write.
Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input Com-
munication Frame, LFRAME, is Low, V
IL
, as Clock
rises and the correct Start cycle is on LAD0-LAD3.
On the following Clock cycles the Host will send
the Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-LAD3.
The memory outputs Sync data until the wait-
states have elapsed.
See
Table 8.
and
Figure 7.
for a description of the
Field definitions for each clock cycle of the trans-
fer. See
Table 23.
and
Figure 11.
for details on the
timings of the signals.
Bus Abort.
The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
V
IL
, during the bus operation; the memory will tri-
state the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received; a Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby.
When LFRAME is High, V
IH
, the mem-
ory is put into Standby mode where LAD0-LAD3
are put into a high-impedance state and the Sup-
ply Current is reduced to the Standby level, I
CC1
.
Reset.
During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, V
IL
. RP or INIT must be held
Low, V
IL
, for t
PLPH
. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset (see
Table 13.
). If RP or
INIT goes Low, V
IL
, during a Program or Erase op-
eration, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to t
PLRH
to abort a Program
or Erase operation.
Block Protection.
Block
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional style interface. The sig-
nals consist of a multiplexed address signals (A0-
Protection
can
be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW080 | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5G | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5T | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5TG | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW080N1 | 功能描述:閃存 3.6V 8M (1Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW080N1G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N1TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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