- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359071 > M50LPW080N5T (意法半導體) 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M50LPW080N5T |
| 廠商： | 意法半導體 |
| 英文描述： | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 8兆1兆× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M50LPW080N5T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
M50LPW080
10/44
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see
Figure
2.
and
Table 1.
.
Input/Output Communications (LAD0-LAD3).
All Input and Output Communication with the
memory take place on these pins. Addresses and
Data for Bus Read and Bus Write operations are
encoded on these pins.
Input Communication Frame (LFRAME).
The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, V
IL
, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
IL
, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, V
IH
, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID1).
The Identification
Inputs (ID0-ID1) allow to address up to 4 memo-
ries on a bus. The value on addresses A20-A21 is
compared to the hardware strapping on the ID0-
ID1 pins to select which memory is being ad-
dressed. For an address bit to be ‘1’ the corre-
spondent ID pin can be left floating or driven Low,
V
IL
; an internal pull-down resistor is included with
a value of R
IL
. For an address bit to be ‘0’ the cor-
respondent ID pin must be driven High, V
IH
; there
will be a leakage current of I
LI2
through each pin
when pulled to V
IH
(see
Table 21.
).
By convention the boot memory must have ID0-
ID1 pins left floating or driven Low, V
IL
and a ‘11’
value on A20-A21 and all additional memories
take sequential ID0-ID1 configuration, as shown in
Table 3.
.
General Purpose Inputs (GPI0-GPI4).
The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, V
IL,
or
High, V
IH
.
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V
IL
; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
;
see
Table 21.
.
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
IL
, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
IH
, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL).
The Top Block Lock in-
put is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL,
is set Low, V
IL
, Program and Block Erase opera-
tions in the Top Block have no effect, regardless of
the state of the Lock Register. When Top Block
Lock, TBL, is set High, V
IH
, the protection of the
Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the
protection of the Main Blocks (Blocks 0 to 14).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP).
The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
set Low, V
IL
, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
WP, is set High, V
IH
, the protection of the Block is
determined by the Lock Register. The state of
相關PDF資料 |
PDF描述 |
|---|---|
| M50LPW080N | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080 | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5G | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5T | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW080N5TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW116N1 | 功能描述:閃存 3.0V 16M (2Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW116N1T | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL/SERL 3V/3.3V 16MBIT 2MX8 40TSOP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。