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參數(shù)資料
| 型號(hào)： | M50LPW080K1G |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 8兆1兆× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁(yè)數(shù)： | 13/44頁(yè) |
| 文件大小： | 641K |
| 代理商： | M50LPW080K1G |
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M50LPW080
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Low Pin
Count (LPC) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read.
Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, V
IH
, and Output Enable, G, Low, V
IL
, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see
Figure 13.
and
Table 25.
for details of when the output becomes
valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, V
IH
and Write En-
able, W, must be Low, V
IL
. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See
Figure 14.
and
Table 26.
for details
of the timing requirements.
Output Disable.
The data outputs are high-im-
pedance when the Output Enable, G, is at V
IH
.
Reset.
During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, V
IL
. RP must be
held Low, V
IL
for t
PLPH
. If RP is goes Low, V
IL
, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to t
PL-
RH
to abort a Program or Erase operation.
Table 5. A/A Mux Bus Operations
Table 6. Manufacturer and Device Codes
Operation
G
W
RP
V
PP
DQ7-DQ0
Bus Read
V
IL
V
IH
V
IH
Don’t Care
Data Output
Bus Write
V
IH
V
IL
V
IH
V
CC
or V
PPH
Data Input
Output Disable
V
IH
V
IH
V
IH
Don’t Care
Hi-Z
Reset
V
IL
or V
IH
V
IL
or V
IH
V
IL
Don’t Care
Hi-Z
Operation
G
W
RP
A19-A1
A0
DQ7-DQ0
Manufacturer Code
V
IL
V
IH
V
IH
V
IL
V
IL
20h
Device Code
V
IL
V
IH
V
IH
V
IL
V
IH
2Fh
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| M50LPW080K1T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K1TG | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K5G | 功能描述:閃存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW080K5T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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