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參數(shù)資料
| 型號： | M50LPW041N |
| 廠商： | 意法半導體 |
| 英文描述： | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 4兆位512KB的× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 6/37頁 |
| 文件大小： | 268K |
| 代理商： | M50LPW041N |
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M50LPW041
6/37
(RP and INIT) are available to put the memory into
a known state.
The data signals, control signal and clock are
designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read.
Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, V
IL
, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 7, LPC Bus Read Field Definitions,
and Figure 5, LPC Bus Read Waveforms, for a de-
scription of the Field definitions for each clock cy-
cle of the transfer. See Table 23, LPC Interface AC
Signal Timing Characteristics and Figure 10, LPC
Interface AC Signal Timing Waveforms, for details
on the timings of the signals.
Bus Write.
Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
After V
CC
becomes valid the Command Interface
is reset to Read mode.
A 0.1μF capacitor should be connected between
the V
CC
Supply Voltage pins and the V
SS
Ground
pin to decouple the current surges from the power
supply. Both V
CC
Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.
V
PP
Optional Supply Voltage.
The V
PP
Optional
Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command description) and Fast Erase options of
the memory. V
PP
can be left floating. When V
PP
=
V
PPH
Fast Program (if a Quadruple Byte Program
Command is performed) and Fast Erase
operations are used.
V
PP
should not be set to V
PPH
for more than 80
hours during the life of the memory.
V
SS
Ground.
V
SS
is the reference for all the volt-
age measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual
interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Interface Bus
Operations below for a description of the bus
operations on each interface.
Low Pin Count (LPC) Bus Operations
The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition
protection against accidental or malicious data
corruption can be achieved using two further
signals (TBL and WP). Finally two reset signals
Table 4. Signal Names (A/A Mux Interface)
IC
Interface Configuration
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
G
Output Enable
W
Write Enable
RC
Row/Column Address Select
RB
Ready/Busy Output
RP
Interface Reset
V
CC
Supply Voltage
V
PP
Optional Supply Voltage for Fast
Program and Fast Erase
Operations
V
SS
Ground
NC
Not Connected Internally
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW041K | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW041 | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N1TG | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N1 | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080N1G | 8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW041N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080 | 制造商:STMicroelectronics 功能描述: |
| M50LPW080K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW080K1 | 功能描述:閃存 3.6V 8M (1Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW080K1G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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