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參數(shù)資料
| 型號： | M50LPW040N1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 4兆位512KB的× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 272K |
| 代理商： | M50LPW040N1T |
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M50LPW040
16/36
Table 14. Low Pin Count Register Configuration Map
(1)
Note: 1. This map is referred to the boot memory (ID0-ID2 floating or driven, L
OW
, V
IL
and A19-A21 set to ‘1’).
Mnemonic
Register Name
Memory
Address
Default
Value
Access
T_BLOCK_LK
Top Block Lock Register (Block 7)
FFBF0002h
01h
R/W
T_MINUS01_LK
Top Block [-1] Lock Register (Block 6)
FFBE0002h
01h
R/W
T_MINUS02_LK
Top Block [-2] Lock Register (Block 5)
FFBD0002h
01h
R/W
T_MINUS03_LK
Top Block [-3] Lock Register (Block 4)
FFBC0002h
01h
R/W
T_MINUS04_LK
Top Block [-4] Lock Register (Block 3)
FFBB0002h
01h
R/W
T_MINUS05_LK
Top Block [-5] Lock Register (Block 2)
FFBA0002h
01h
R/W
T_MINUS06_LK
Top Block [-6] Lock Register (Block 1)
FFB90002h
01h
R/W
T_MINUS07_LK
Top Block [-7] Lock Register (Block 0)
FFB80002h
01h
R/W
GPI_REG
General Purpose Input Register
FFBC0100h
N/A
R
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down.
The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
General Purpose Input Register
The General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0-
GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writ-
ing to it has no effect.
The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct
data is read.
Write Lock.
The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When V
PP
is less than V
PPLK
all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, V
IL
, then the Top Block (Block 7) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, V
IL
, then the Main
Blocks (Blocks 0 to 6) are write protected and can-
not be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock.
The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
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| M50LPW041K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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