參數(shù)資料
型號： M50LPW002
廠商： 意法半導體
英文描述： 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述： 2兆位的256Kb × 8，啟動塊3V電源低引腳數(shù)快閃記憶體
文件頁數(shù)： 9/39頁
文件大?。?/td> 258K
代理商： M50LPW002
9/39
M50LPW002
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual
interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Interface Bus
Operations below for a description of the bus
operations on each interface.
Low Pin Count (LPC) Bus Operations
The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition
protection against accidental or malicious data
corruption can be achieved using two further
signals (TBL and WP). Finally two reset signals
(RP and INIT) are available to put the memory into
a known state.
The data signals, control signal and clock are
designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read.
Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, V
IL
, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 5, Bus Read Field Definitions (LPC
Interface), and Figure 5, Bus Read Waveforms
(LPC Interface), for a description of the Field defi-
nitions for each clock cycle of the transfer. See Ta-
ble 22, AC Signal Timing Characteristics (LPC
Interface), and Figure 10, AC Signal Timing Wave-
forms (LPC Interface), for details on the timings of
the signals.
Bus Write.
Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input
Communication Frame, LFRAME, is Low, V
IL
, as
Clock rises and the correct Start cycle is on LAD0-
LAD3. On the following Clock cycles the Host will
send the Cycle Type + Dir, Address, other control
bits, Data0-Data3 and Data4-Data7 on LAD0-
LAD3. The memory outputs Sync data until the
wait-states have elapsed.
Refer to Table 6, Bus Write Field Definitions (LPC
Interface), and Figure 6, Bus Write Waveforms
(LPC Interface), for a description of the Field
definitions for each clock cycle of the transfer. See
Table 22, AC Signal Timing Characteristics (LPC
Interface), and Figure 10, AC Signal Timing
Waveforms (LPC Interface), for details on the
timings of the signals.
Bus Abort.
The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
V
IL
, during the bus operation; the memory will tri-
state the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the
Command
Interface
command as soon as the data is fully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
Standby.
When LFRAME is High, V
IH
, the
memory is put into Standby mode where LAD0-
LAD3 are put into a high-impedance state and the
Supply Current is reduced to the Standby level,
I
CC1
.
Reset.
During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, V
IL
. RP or INIT must be held
Low, V
IL
, for t
PLPH
. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 13. If RP or
INIT goes Low, V
IL
, during a Program or Erase
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the memory can take up to t
PLRH
to abort a
Program or Erase operation.
Block Protection.
Block
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
starts
executing
the
Protection
can
be
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M50LPW002K 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
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M50LPW012K 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
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