- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377829 > M50FLW080BNB5TP (意法半導(dǎo)體) 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M50FLW080BNB5TP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| 中文描述： | 8兆位（13 × 64KB之座3 × 16 × 4KB的部門），3V電源固件集線器/低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 341K |
| 代理商： | M50FLW080BNB5TP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Signal descriptions
M50FLW080A, M50FLW080B
14/64
2.1.4
General-purpose inputs (GPI0-GPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read, with their
contents being available in the General Purpose Inputs Register. The pins must have stable
data throughout the entire cycle that reads the General Purpose Input Register. These pins
should be driven Low, V
IL,
or High, V
IH
, and must not be left floating.
2.1.5
Interface configuration (IC)
The Interface Configuration input selects whether the FWH/LPC interface or the
Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during operation of the memory device, except for
selecting the desired interface in the period before power-up or during a Reset.
To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or
driven Low, V
IL
. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin
should be driven High, V
IH
. An internal pull-down resistor is included with a value of R
IL
;
there will be a leakage current of I
LI2
through each pin when pulled to V
IH
.
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is
driven Low, V
IL
, the memory is in Reset mode (the outputs go to high impedance, and the
current consumption is minimized). When RP is driven High, V
IH
, the device is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
CPU Reset (INIT)
The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI
specification.
2.1.9
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.
When Top Block Lock, TBL, is driven Low, V
IL
, program and erase operations in the Top
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is driven High, V
IH
, the protection of the Block is determined by the Lock Registers.
The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks
0 to 14). For details, see
Appendix A
.
Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and
must not be changed until the operation has completed, otherwise unpredictable results
may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50FLW080AK5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AK5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FW002 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Firmware Hub Flash Memory |
| M50FW002K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Firmware Hub Flash Memory |
| M50FW002K1 | 功能描述:閃存 3.6V 2M (256Kx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FW002K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Firmware Hub Flash Memory |
| M50FW002K5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Firmware Hub Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。