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參數(shù)資料
| 型號： | M50FLW080BK5P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| 中文描述： | 8兆位（13 × 64KB之座3 × 16 × 4KB的部門），3V電源固件集線器/低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 22/64頁 |
| 文件大小： | 341K |
| 代理商： | M50FLW080BK5P |
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Bus operations
M50FLW080A, M50FLW080B
22/64
Table 8.
Figure 8.
LPC Bus Read waveforms (1-byte)
LPC Bus Read field definitions (1-byte)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
2
1
CYCTYPE
+ DIR
0100b
I
Indicates the type of cycle and selects 1-byte
reading. Bits 3:2 must be 01b. Bit 1 indicates
the direction of transfer: 0b for read. Bit 0 is
Don’t Care.
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set
to 1. A22=1 for memory access, and A22=0
for register access.
Table 5
shows the
appropriate values for A21-A20.
11
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
12
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of
LAD0-LAD3 during this cycle.
13-14
2
WSYNC
0101b
O
The LPC Flash Memory drives LAD0-LAD3
to 0101b (short wait-sync) for two clock
cycles, indicating that the data is not yet
available. Two wait-states are always
included.
15
1
RSYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3
to 0000b, indicating that data will be available
during the next clock cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with
the least significant nibble.
18
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3
to 1111b to indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs, the
host takes control of LAD0-LAD3.
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
TAR
SYNC
DATA
TAR
1
1
8
2
3
2
2
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| M50FLW080BK5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BNB5P | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BNB5TP | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FLW080BK5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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| M50FLW080BK5TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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