參數(shù)資料
型號(hào)： M50FLW080ANB5P
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
中文描述： 8兆位（13 × 64KB之座3 × 16 × 4KB的部門(mén)），3V電源固件集線器/低引腳數(shù)快閃記憶體
文件頁(yè)數(shù)： 17/64頁(yè)
文件大小： 341K
代理商： M50FLW080ANB5P
M50FLW080A, M50FLW080B
Bus operations
17/64
3
Bus operations
The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different
bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full
functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for
erase and program operations.
See the sections below, The
Firmware Hub/low-pin-count (FWH/LPC) bus operations
and
Address/Address multiplexed (A/A Mux) bus operations
, for details of the bus operations on
each interface.
3.1
Firmware Hub/low-pin-count (FWH/LPC) bus operations
The M50FLW080 automatically identifies the type of FWH/LPC protocol from the first
received nibble (START nibble) and decodes the data that it receives afterwards, according
to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface
consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME)
and a clock (CLK).
Protection against accidental or malicious data corruption is achieved using two additional
signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory
into a known state.
The data, control and clock signals are designed to be compatible with PCI electrical
specifications. The interface operates with clock speeds of up to 33MHz.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Standby, Reset and Block Protection.
3.1.1
Bus Read
Bus Read operations are used to read from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when the Input Communication Frame,
FWH4/LFRAME, is Low, V
IL
, and the correct Start cycle is present on FWH0/LAD0-
FWH3/LAD3. On subsequent clock cycles the Host will send to the memory:
ID Select, Address and other control bits on FWH0-FWH3 in FWH mode.
Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode.
●
●
The device responds by outputting Sync data until the wait states have elapsed, followed by
Data0-Data3 and Data4-Data7.
See
Table 6
and
Table 8
, and
Figure 6
and
Figure 8
, for a description of the Field definitions
for each clock cycle of the transfer. See
Table 26
, and
Figure 14
, for details on the timings of
the signals.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FLW080ANB5T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080ANB5TG 功能描述:閃存 8 Mbit RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M50FLW080ANB5TP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080AXW21/I 功能描述:閃存 8-bit MCU 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M50FLW080AYW21 功能描述:閃存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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