參數(shù)資料
型號(hào): M50FLW080AN5TP
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
中文描述: 8兆位(13 × 64KB之座3 × 16 × 4KB的部門(mén)),3V電源固件集線器/低引腳數(shù)快閃記憶體
文件頁(yè)數(shù): 23/64頁(yè)
文件大?。?/td> 341K
代理商: M50FLW080AN5TP
M50FLW080A, M50FLW080B
Bus operations
23/64
Table 9.
Figure 9.
LPC Bus Write waveforms (1 byte)
LPC Bus Write field definitions (1 byte)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
2
1
CYCTYPE
+ DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be
01b. Bit 1 indicates the direction of transfer: 1b
for write. Bit 0 is don’t care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to
1. A22=1 for memory access, and A22=0 for
register access.
Table 5
shows the appropriate
values for A21-A20.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the
least significant nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1
1
8
2
2
1
2
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