參數(shù)資料
型號: M50FLW040BNB5TG
廠商: 意法半導體
英文描述: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
中文描述: 4兆位(5 × 64KB之座3 × 16 × 4KB的部門)3V電源固件集線器/低引腳數(shù)快閃記憶體
文件頁數(shù): 17/52頁
文件大小: 417K
代理商: M50FLW040BNB5TG
17/52
M50FLW040A, M50FLW040B
Table 9. LPC Bus Write Field Definitions (1 Byte)
Figure 10. LPC Bus Write Waveforms (1 Byte)
Table 10. A/A Mux Bus Operations
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
2
1
CYCTY
PE +
DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don
t
care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access.
Table 5.
shows the
appropriate values for A21-A19.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
Operation
G
W
RP
V
PP
DQ7-DQ0
Bus Read
V
IL
V
IH
V
IH
Don't Care
Data Output
Bus Write
V
IH
V
IL
V
IH
V
CC
or V
PPH
Data Input
Output Disable
V
IH
V
IH
V
IH
Don't Care
Hi-Z
Reset
V
IL
or V
IH
V
IL
or V
IH
V
IL
Don't Care
Hi-Z
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1
1
8
2
2
1
2
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