- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377828 > M50FLW040BK1G (意法半導(dǎo)體) 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | M50FLW040BK1G |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| 中文描述： | 4兆位（5 × 64KB之座3 × 16 × 4KB的部門(mén)）3V電源固件集線器/低引腳數(shù)快閃記憶體 |
| 文件頁(yè)數(shù)： | 10/52頁(yè) |
| 文件大小： | 417K |
| 代理商： | M50FLW040BK1G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)
M50FLW040A, M50FLW040B
10/52
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on
this device. The active interface is selected before
power-up, or during Reset, using the Interface
Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub/Low Pin Count (FWH/LPC) Signal
Descriptions
section and the
Address/Address
Multiplexed (A/A Mux) Signal Descriptions
sec-
tion, respectively, while the supply signals are dis-
cussed in the
Supply Signal Descriptions
section.
Firmware Hub/Low Pin Count (FWH/LPC)
Signal Descriptions
Please see
Figure 2.
and
Table 1.
.
Input/Output Communications (FWH0/LAD0-
FWH3/LAD3).
All Input and Output Communica-
tions with the memory take place on these pins.
Addresses and Data for Bus Read and Bus Write
operations are encoded on these pins.
Input
Communication
LFRAME).
The Input Communication Frame
(FWH4/LFRAME) signal indicates the start of a
bus operation. When Input Communication Frame
is Low, V
IL
, on the rising edge of the Clock, a new
bus operation is initiated. If Input Communication
Frame is Low, V
IL
, during a bus operation then the
operation is aborted. When Input Communication
Frame is High, V
IH
, the current bus operation is ei-
ther proceeding or the bus is idle.
Identification Inputs (ID0-ID3).
Up to 16 memo-
ries can be addressed on a bus, in the Firmware
Hub (FWH) mode. The Identification Inputs allow
each device to be given a unique 4-bit address. A
‘
0
’
is signified on a pin by driving it Low, V
IL
, or
leaving it floating (since there is an internal pull-
down resistor, with a value of R
IL
). A
‘
1
’
is signified
on a pin by driving it High, V
IH
(and there will be a
leakage current of I
LI2
through the pin).
By convention, the boot memory must have ad-
dress
‘
0000
’
, and all additional memories are giv-
en addresses, allocated sequentially, from
‘
0001
’
.
In the Low Pin Count (LPC) mode, the identifica-
tion Inputs (ID0-ID2) can address up to 8 memo-
ries on a bus. In the LPC mode, the ID3 pin is
Reserved for Future Use (RFU). The value on ad-
dress A19-A21 is compared to the hardware strap-
ping on the ID0-ID2 pins to select the memory that
is being addressed. For an address bit to be
‘
1
’
,
the corresponding ID pin can be left floating or
driven Low, V
IL
(again, with the internal pull-down
resistor, with a value of R
IL
). For an address bit to
be
‘
0
’
, the corresponding ID pin must be driven
High, V
IH
(and there will be a leakage current of
I
LI2
through the pin, as specified in
Table 24.
). For
details, see
Table 5.
.
Frame
(FWH4/
General Purpose Inputs (GPI0-GPI4).
The
General Purpose Inputs can be used as digital in-
puts for the CPU to read, with their contents being
available in the General Purpose Inputs Register.
The pins must have stable data throughout the en-
tire cycle that reads the General Purpose Input
Register. These pins should be driven Low, V
IL,
or
High, V
IH
, and must not be left floating.
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the FWH/LPC in-
terface or the Address/Address Multiplexed (A/A
Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during
operation of the memory device, except for select-
ing the desired interface in the period before pow-
er-up or during a Reset.
To select the FWH/LPC Interface, the Interface
Configuration pin should be left to float or driven
Low, V
IL
. To select the Address/Address Multi-
plexed (A/A Mux) Interface, the pin should be driv-
en High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
.
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the device. When Interface
Reset (RP) is driven Low, V
IL
, the memory is in
Reset mode (the outputs go to high impedance,
and the current consumption is minimized). When
RP is driven High, V
IH
, the device is in normal op-
eration. After exiting Reset mode, the memory en-
ters Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, signal
is used to Reset the device when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3.
The Clock conforms to the PCI specification.
Top Block Lock (TBL).
The Top Block Lock in-
put is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is
driven Low, V
IL
, program and erase operations in
the Top Block have no effect, regardless of the
state of the Lock Register. When Top Block Lock,
TBL, is driven High, V
IH
, the protection of the Block
is determined by the Lock Register. The state of
Top Block Lock, TBL, does not affect the protec-
tion of the Main Blocks (Blocks 0 to 6). For details,
see
APPENDIX A.
.
Top Block Lock, TBL, must be set prior to a pro-
gram or erase operation being initiated, and must
not be changed until the operation has completed,
otherwise unpredictable results may occur. Simi-
larly, unpredictable behavior is possible if WP is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50FLW040BK1P | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AK1G | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AK1P | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AK1T | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040AK1TG | 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FLW040BK1P | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040BK1T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040BK1TG | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040BK1TP | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW040BK5 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。