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    參數(shù)資料
    型號: M5-384/160-12HC
    廠商: LATTICE SEMICONDUCTOR CORP
    元件分類: PLD
    英文描述: Fifth Generation MACH Architecture
    中文描述: EE PLD, 12 ns, PQFP208
    封裝: HEAT SINK, PLASTIC, QFP-208
    文件頁數(shù): 2/47頁
    文件大?。?/td> 1145K
    代理商: M5-384/160-12HC
    10
    MACH 5 Family
    MULTIPLE I/O AND DENSITY OPTIONS
    The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers
    to choose a device close to their logic density and I/O requirements, thus minimizing costs. For
    the same package type, every density has the same pin-out. With proper design considerations, a
    design can be moved to a higher or lower density part as required.
    IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY
    Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard.
    This allows functional testing of the circuit board on which the device is mounted through a serial
    scan path that can access all critical logic nodes. Internal registers are linked internally, allowing
    test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and
    shifted out for verication. In addition, these devices can be linked into a board-level serial scan
    path for more complete board-level testing.
    IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING
    Programming devices in-system provides a number of signicant benets including: rapid
    prototyping, lower inventory levels, higher quality, and the ability to make in-eld modications.
    All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1-
    compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan
    Test Access Port as the communication interface through which ISP is achieved, customers get the
    benet of a standard, well-dened interface.
    MACH 5 devices can be programmed across the commercial temperature and voltage range. The
    PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO
    software takes the JEDEC le output produced by design implementation software, along with
    information about the Boundary Scan chain, and creates a set of vectors that are used to drive the
    Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain
    via the parallel port of a PC. Alternatively, LatticePRO software can output les in formats
    understood by common automated test equipment. This equipment can then be used to program
    MACH 5 devices during the testing of a circuit board.
    PCI COMPLIANT
    MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus
    Specication version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are
    fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to
    clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MACH 5
    devices provide the speed, drive, density, output enables and I/Os for the most complex PCI
    designs.
    相關(guān)PDF資料
    PDF描述
    M5-384/160-12HI Fifth Generation MACH Architecture
    M5-384/160-15HC Fifth Generation MACH Architecture
    M5-384/160-15HI Fifth Generation MACH Architecture
    M5-384/160-20HI Fifth Generation MACH Architecture
    M5-384/160-6HC Fifth Generation MACH Architecture
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