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參數(shù)資料
| 型號(hào)： | M5-384/160-10HI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 10 ns, PQFP208 |
| 封裝： | HEAT SINK, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 6/47頁(yè) |
| 文件大?。?/td> | 1145K |
| 代理商： | M5-384/160-10HI |
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14
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-128/XXX
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
S E G M E N T I N T E R C O N N E C T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT 0
SEGMENT 1
I0, 1
I2, 3
2
20446G-007
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