參數(shù)資料
型號: M5-256/68-7YC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: Fifth Generation MACH Architecture
中文描述: EE PLD, 7.5 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 46/47頁
文件大小: 1145K
代理商: M5-256/68-7YC
8
MACH 5 Family
OE Generator
There is one output enable (OE) generator per PAL block that generates two product-term driven
output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can
choose to be permanently enabled, permanently disabled, or choose one of the two product term
output enables per PAL block (Figure 6).
Output Enable
Generator
VCC
Internal Feedback
External Feedback
20446G-006
Figure 6. Output Enable Generator and I/O Cell
相關(guān)PDF資料
PDF描述
M5-256/68-7YI Fifth Generation MACH Architecture
M5-320/160-15HC Fifth Generation MACH Architecture
M5-320/160-15HI Fifth Generation MACH Architecture
M5-320/160-7HC Fifth Generation MACH Architecture
M5-320/160-7HI Fifth Generation MACH Architecture
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