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參數(shù)資料
| 型號： | M4LV-128/64-18YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 18 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M4LV-128/64-18YI |
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20
MACH 4 Family
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY
All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant
to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the
device is mounted through a serial scan path that can access all critical logic nodes. Internal
registers are linked internally, allowing test data to be shifted in and loaded directly onto test
nodes, or test node data to be captured and shifted out for verication. In addition, these devices
can be linked into a board-level serial scan path for more complete board-level testing.
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of signicant benets including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-eld modications.
All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary
ScanTest Access Ports. This capability has been implemented in a manner that ensures that the
port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication
interface through which ISP is achieved, customers get the benet of a standard, well-dened
interface.
MACH 4 devices can be programmed across the commercial temperature and voltage range. The
PC-based LatticePRO software facilitates in-system programming of MACH 4 devices. LatticePRO
takes the JEDEC le output produced by the design implementation software, along with
information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG
chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a
PC. Alternatively, LatticePRO software can output les in formats understood by common
automated test equipment. This equpment can then be used to program MACH 4 devices during
the testing of a circuit board.
PCI COMPLIANT
MACH 4 devices in the -7/-10/-12 speed grades are compliant with the PCI Local Bus
Specication version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are
fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition
to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs.
The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they
accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the
5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed-
voltage design capability.
BUS-FRIENDLY INPUTS AND I/OS
All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating
two inverters in series which loop back to the input. This double inversion weakly holds the
input at its last driven logic state. While it is good design practice to tie unused pins to a known
state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where
noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a
logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance
Characteristics on the Lattice/Vantis Data Book CD-ROM or Lattice web site.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M4LV-128/64-7VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-7YC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-256/128-18AI | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-256/128-18YI | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-256/128-7AC | High Performance E 2 CMOS In-System Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M4LV-128N/64-10JC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| M4LV-128N/64-10JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| M4LV-128N/64-12JC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| M4LV-128N/64-12JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| M4LV-128N/64-14JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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