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參數(shù)資料
| 型號： | M4A5-96/48-7VC |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD ISP 4A 96MC 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispMACH® 4A |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 96 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
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ispMACH 4A Family
3
GENERAL DESCRIPTION
The ispMACH 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior
Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market,
greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512
macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-
xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test equipment for
device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention
after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver
guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when
using up to 20 product terms per output (Table 2).
Note:
1. C = Commercial,
I = Industrial
Table 2. ispMACH 4A Speed Grades
Device
Speed Grade
-5
-55
-6
-65
-7
-10
-12
-14
M4A3-32
M4A5-32
C
C, I
I
M4A3-64/32
M4A5-64/32
C
C, I
I
M4A3-64/64
C
C, I
I
M4A3-96
M4A5-96
C
C, I
I
M4A3-128
M4A5-128
C
C, I
I
M4A3-192
M4A5-192
C
C, I
I
M4A3-256/128
C
C, I
I
M4A5-256/128
C
C, I
I
M4A3-256/192
M4A3-256/160
C
C, I
I
M4A3-384
C
C, I
I
M4A3-512
C
C, I
I
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