參數(shù)資料
型號: M4A5-96/48-55VNC
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 3/62頁
文件大?。?/td> 0K
描述: IC CPLD 96MACRO 100TQFP
標準包裝: 90
系列: ispMACH® 4A
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 5.5ns
電壓電源 - 內部: 4.75 V ~ 5.25 V
宏單元數(shù): 64
輸入/輸出數(shù): 48
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-TQFP(14x14)
包裝: 托盤
ispMACH 4A Family
11
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
DQ
AP AR
DQ
AP AR
LQ
AP AR
LQ
AP AR
G
TQ
AP AR
17466G-011
Figure 6. Primary Macrocell Congurations
g. Combinatorial with programmable polarity
a. D-type with XOR
b. D-type with programmable D polarity
c. Latch with XOR
d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR
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