參數(shù)資料
型號: M48Z2M1V
廠商: 意法半導體
英文描述: 16Mb (2Mb x 8) ZEROPOWER SRAM(16Mb零功耗SRAM)
中文描述: 16Mb的(含2Mb × 8)ZEROPOWER的SRAM(16Mb的零功耗的SRAM)
文件頁數(shù): 1/17頁
文件大小: 308K
代理商: M48Z2M1V
1/17
March 2005
M48Z2M1Y
M48Z2M1V
5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER
SRAM
FEATURES SUMMARY
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z2M1Y: V
CC
= 4.5 to 5.5V
4.2V
V
PFD
4.5V
M48Z2M1V: V
CC
= 3.0 to 3.6V
2.8V
V
PFD
3.0V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2Mb x 8 SRAMs
Figure 1. 36-pin, DIP Module
PLDIP36 (PL)
Module
36
1
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