參數(shù)資料
型號(hào): M48T59Y-70MH1
廠商: STMICROELECTRONICS
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.330 INCH, PLASTIC, SOH-28
文件頁(yè)數(shù): 32/32頁(yè)
文件大小: 373K
代理商: M48T59Y-70MH1
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
M48T59, M48T59Y, M48T59V
Operation modes
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 5.
Read mode AC waveforms
Note:
WRITE enable (W) = High.
Table 3.
Read mode AC characteristics
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where
noted).
M48T59/Y/V
Unit
–70
Min
Max
tAVAV
READ cycle time
70
ns
tAVQV
(2)
2.
CL = 100pF (see Figure 13 on page 22).
Address valid to output valid
70
ns
Chip enable low to output valid
70
ns
tGLQV
Output enable low to output valid
35
ns
tELQX
(3)
3.
CL = 5pF (see Figure 13 on page 22).
Chip enable low to output transition
5
ns
tGLQX
Output enable low to output transition
5
ns
tEHQZ
Chip enable high to output Hi-Z
25
ns
tGHQZ
Output enable high to output Hi-Z
25
ns
tAXQX
Address transition to output transition
10
ns
AI01385
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E
G
DQ0-DQ7
VALID
相關(guān)PDF資料
PDF描述
M48T59V-70MH6 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T59V-70MH6E REAL TIME CLOCK, PDSO28
M48T59V-70MH6TR 0 TIMER(S), REAL TIME CLOCK, PDSO28
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