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參數(shù)資料
| 型號： | M48T59V-70MH1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 373K |
| 代理商： | M48T59V-70MH1 |
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M48T59, M48T59Y, M48T59V
Operation modes
Table 4.
Write mode AC characteristics
2.3
Data retention mode
With valid VCC applied, the M48T59/Y/V operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T59/Y/V may respond to transient noise spikes on VCC that
reach into the deselect window during the time the device is sampling VCC. Therefore,
decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T59/Y/V for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected and the power
supply is switched to external VCC. Deselect continues for trec after VCC reaches VPFD
(max).
For more information on Battery Storage Life refer to the Application Note AN1012.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
M48T59/Y/V
Unit
–70
Min
Max
tAVAV
WRITE cycle time
70
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
50
ns
tELEH
Chip enable low to chip enable high
55
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
(2)(3)
2.
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z
25
ns
tAVWH
Address valid to WRITE enable high
60
ns
tAVEH
Address valid to chip enable high
60
ns
tWHQX
WRITE enable high to output transition
5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T59Y-70MH1E | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59Y-70MH1 | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59V-70MH6 | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59V-70MH6E | REAL TIME CLOCK, PDSO28 |
| M48T59V-70MH6TR | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T59V-70MH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70MH1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70MH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T59V-70MH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T59V-70MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
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