參數(shù)資料
型號: M48T513Y-85PL1
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA36
封裝: PLASTIC, MODULE, DIP-36
文件頁數(shù): 26/31頁
文件大?。?/td> 168K
代理商: M48T513Y-85PL1
M48T513Y, M48T513V
4/31
DESCRIPTION
The M48T513Y/V TIMEKEEPER RAM is a
512 Kb x 8 non-volatile static RAM and real time
clock, with programmable alarms and a watchdog
timer. The special DIP package provides a fully in-
tegrated battery back-up memory and real time
clock solution. The M48T513Y/V directly replaces
industry standard 512 Kb x 8 SRAM. It also pro-
vides the non-volatility of Flash without any re-
quirement for special WRITE timing or limitations
on the number of WRITEs that can be performed.
For surface mount environments ST provides a
Chip Set solution consisting of a 44-pin, 330mil
SOIC TIMEKEEPER SUPERVISOR (M48T201V/
Y) and a 32-pin TSOP Type II (10 x 20mm)
LPSRAM (M68Z512/W) packages.
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Txx-BR12SH1” (see
Table 15, page 24).
Figure 3. Logic Diagram
Table 1. Signal Names
AI02308
19
A0-A18
DQ0-DQ7
VCC
M48T513Y
M48T513V
G
VSS
8
E
W
RST
IRQ/FT
RSTIN
WDI
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
WDI
Watchdog input
RST
Reset Output (open drain)
RSTIN
Reset Input
IRQ/FT
Interrupt / Frequency Test
Output (open drain)
VCC
Supply Voltage
VSS
Ground
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