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參數(shù)資料
| 型號(hào)： | M48T513Y-70CS1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| 封裝： | SNAPHAT, PLASTIC, SO-44 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 168K |
| 代理商： | M48T513Y-70CS1 |
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M48T513Y, M48T513V
Power-on Reset
The M48T513Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD. The
RST pin is an open drain output and an appropri-
ate pull-up resistor to VCC should be chosen to
control the rise time.
Reset Input (RSTIN)
The M48T513Y/V provides an independent input
which can generate an output reset. The duration
and function of this reset is identical to a reset gen-
erated by a power cycle. Table 13 and Figure 15
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tR will not generate a re-
set condition. RSTIN is internally pulled up to VCC
through a 100K
resistor.
Battery Low Warning
The M48T513Y/V automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied.
The M48T513Y/V only monitors the battery when
a nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Initial Power-on Defaults
Upon application of power to the device, the fol-
lowing register bits are set to a ’0’ state: WDS,
BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
Figure 15. RSTIN Timing Waveform
Table 13. Reset AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure Figure 7, page 8)
Symbol
Parameter(1)
Min
Max
Unit
tR
RSTIN Low to RST Low
20
100
ms
tRHRZ
(2)
RSTIN High to RST Hi-Z
40
200
ms
AI02585
tRHRZ
RSTIN
RST
tR
Hi-Z
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相關(guān)代理商/技術(shù)參數(shù) |
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| M48T513Y-70PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y-85CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513Y-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513YPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
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