參數(shù)資料
型號: M48T513V-85PL1
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA36
封裝: PLASTIC, MODULE, DIP-36
文件頁數(shù): 5/31頁
文件大小: 169K
代理商: M48T513V-85PL1
13/31
M48T513Y, M48T513V
WRITE Mode
The M48T513Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
Figure 10. WRITE Enable Controlled, WRITE AC Waveforms
Figure 11. Chip Enable Controlled, WRITE AC Waveforms
AI02382
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI02582
tAVAV
tEHAX
tDVWH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEL
tAVWL
tELEH
tWHDX
DATA INPUT
相關(guān)PDF資料
PDF描述
M48T513Y-70PM1 0 TIMER(S), REAL TIME CLOCK, PDIP36
M48T513V-85PM1 0 TIMER(S), REAL TIME CLOCK, PDIP36
M62320GP 8 I/O, PIA-GENERAL PURPOSE, PDSO16
M62320P 8 I/O, PIA-GENERAL PURPOSE, PDIP16
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