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參數資料
| 型號： | M48T37Y-70MH6TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數據恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44 |
| 文件頁數： | 3/30頁 |
| 文件大小： | 515K |
| 代理商： | M48T37Y-70MH6TR |
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M48T37Y, M48T37V
Operation modes
Doc ID 7019 Rev 9
Table 4.
WRITE mode AC characteristics
2.3
Data retention mode
With valid VCC applied, the M48T37Y/V operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF.
The M48T37Y/V may respond to transient noise spikes on VCC that reach into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended. When VCC drops below VSO, the control circuit switches
power to the internal battery which preserves data and powers the clock. The internal button
cell will maintain data in the M48T37Y/V for an accumulated period of at least 7 years at
room temperature when VCC is less than VSO. As system power returns and VCC rises
above VSO, the battery is disconnected and the power supply is switched to external VCC.
Normal RAM operation can resume tREC after VCC reaches VPFD (max).
For more information on battery storage life refer to the application note AN1012.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V
(except where noted).
M48T37Y
M48T37V
Unit
–70
–100
Min
Max
Min
Max
tAVAV
WRITE cycle time
70
100
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
50
80
ns
tELEH
Chip enable low to chip enable high
55
80
ns
tWHAX
WRITE enable high to address transition
0
10
ns
tEHAX
Chip enable high to address transition
0
10
ns
tDVWH
Input valid to WRITE enable high
30
50
ns
tDVEH
Input valid to chip enable high
30
50
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
(2)(3)
2.
CL = 5 pF.
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z
25
50
ns
tAVWH
Address valid to WRITE enable high
60
80
ns
tAVEH
Address valid to chip enable high
60
80
ns
tWHQX
WRITE enable high to output transition
5
10
ns
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相關代理商/技術參數 |
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|---|---|
| M48T37YMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
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| M48T39Y-100PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kb 32K x8 TIMEKEEPER SRAM |
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