參數(shù)資料
型號(hào)： M48T37V-70MH6E
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO44
封裝： 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOIC-44
文件頁(yè)數(shù)： 28/29頁(yè)
文件大?。?/td> 276K
代理商： M48T37V-70MH6E
Operation modes
M48T37Y, M48T37V
2
Operation modes
As Figure 3 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that
provide user accessible BYTEWIDE clock information are in the bytes with addresses
7FF1 and 7FF9h-7FFFh (located in Table 5 on page 13). The clock locations contain the
century, year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are
made automatically.
Byte 7FF8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-
control microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are
reserved for clock alarm programming. These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin when the alarm bytes match the date,
hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock
counters themselves; they are memory locations consisting of BiPORT READ/WRITE
memory cells. The M48T37Y/V includes a clock control circuit which updates the clock
bytes with current information once per second. The information can be accessed by the
user in the same manner as any other location in the static memory array.
The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below the
Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Note:
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2.1
Read mode
The M48T37Y/V is in the READ Mode whenever WRITE Enable (W) is high and Chip
Enable (E) is low. The unique address specified by the 15 Address Inputs defines which one
of the 32,752 bytes of data is to be accessed. Valid data will be available at the Data I/O
pins within Address Access time (tAVQV) after the last address input signal is stable,
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.5 to 5.5V
or
3.0 to 3.6V
VIH
X
High Z
Standby
WRITE
VIL
XVIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(1)
1.
See Table 13 on page 23 for details.
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
High Z
Battery Back-up
Mode
相關(guān)PDF資料
PDF描述
M48T37V-70MH6 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48T37Y-70MH1F 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48T37Y-70MH6TR 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48T37Y-70MH1E 0 TIMER(S), REAL TIME CLOCK, PDSO44
M48T37V-10MH1E 0 TIMER(S), REAL TIME CLOCK, PDSO44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M48T37V-70MH6F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T37V-70MH6TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T37VMH 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T37VSH 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
M48T37Y 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
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