參數(shù)資料
型號(hào): M48T37V-10MH6TR
廠(chǎng)商: STMICROELECTRONICS
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44
文件頁(yè)數(shù): 9/30頁(yè)
文件大?。?/td> 515K
代理商: M48T37V-10MH6TR
M48T37Y, M48T37V
Clock operations
Doc ID 7019 Rev 9
The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the
watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to
the watchdog register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied. The WDI pin should be connected to VSS if not used.
3.7
Power-on reset
The M48T37Y/V continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC
passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and
an appropriate resistor to VCC should be chosen to control rise time (see Figure 13 on
3.8
Programmable interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an
interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the flag register
7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the watchdog steering
(WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.
The alarm flag and the IRQ/FT output are cleared by a READ to the flags register. An
interrupt condition reset will not occur unless the addresses are stable at the flag location for
at least 15 ns while the device is in the READ mode as shown in Figure 7 on page 14.
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 k
Ω
recommended) to VCC. The pin remains in the high impedance state unless an interrupt
occurs or the frequency test mode is enabled.
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