參數(shù)資料
型號: M48T212Y-70MH1TR
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, PLASTIC, SOH-44
文件頁數(shù): 3/32頁
文件大?。?/td> 473K
代理商: M48T212Y-70MH1TR
11/32
M48T212Y, M48T212V
WRITE Mode
The M48T212Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are in a
low state after the address inputs are stable. The
start of a WRITE is referenced from the latter oc-
curring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The
addresses must be held valid throughout the cy-
cle. E or W must return high for a minimum of tE-
HAX from Chip Enable or tWHAX from WRITE
Enable prior to the initiation of another READ or
WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX af-
terward.
G should be kept high during WRITE cycles to
avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on
W will disable the outputs tWLQZ after W falls.
When E is low during the WRITE, one of the on-
board TIMEKEEPER registers will be selected
and data will be written into the device. When EX
is low (and E is high) an external SRAM location is
selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms
Note: EX is assumed High.
AI02641
W
DQ0-DQ7
G
DATA IN
VALID
ADDRESS
tAVAV
E
tAVEH
tAVAV
WRITE
READ
DATA OUT
VALID
DATA OUT
VALID
tAVWH
tAVQV
tWLWH
tWHDX
tWHAX
tWHQX
tWLQZ
tDVWH
tGLQV
tEHQZ
tDVEH
DATA IN
VALID
tELEH
tEHAX
tAVEL
tEHDX
tAVWL
相關(guān)PDF資料
PDF描述
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