參數(shù)資料
型號(hào)： M48T212V-85MH1F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO44
封裝： 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44
文件頁(yè)數(shù)： 6/35頁(yè)
文件大小： 348K
代理商： M48T212V-85MH1F
Obsolete
Product(s)
- Obsolete
Product(s)
Operation
M48T212V
Table 6.
Write mode AC characteristics
2.4
Data retention mode
With valid VCC applied, the M48T212V can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M48T212V will automatically deselect,
write protecting itself (and any external SRAM) when VCC falls between VPFD (max) and
VPFD (min). This is accomplished by internally inhibiting access to the clock registers via the
E signal. At this time, the Reset pin (RST) is driven active and will remain active until VCC
returns to nominal levels.
External RAM access is inhibited in a similar manner by forcing E1CON and E2CON to a high
level. This level is within 0.2 volts of the VBAT. E1CON and E2CON will remain at this level as
long as VCC remains at an out-of-tolerance condition.
When VCC falls below battery back-up switchover voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT
battery and the clock registers and external SRAM are
maintained from the attached battery supply. All outputs become high impedance. The VOUT
pin is capable of supplying 100A of current to the attached memory with less than 0.3V
drop under this condition. On power up, when VCC returns to a nominal value, write
protection continues for 200ms (max) by inhibiting E1CON or E2CON.
The RST signal also remains active during this time (see Figure 14 on page 29).
Note:
Most low power SRAMs on the market today can be used with the M48T212V
TIMEKEEPER SUPERVISOR. There are, however some criteria which should be used in
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).
M48T212V
Unit
–85
Min
Max
tAVAV
Write cycle time
85
ns
tAVWL
Address valid to write enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
Write enable pulse width
55
ns
tELEH
Chip enable low to chip enable high
60
ns
tWHAX
Write enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to write enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
Write enable high to input transition
0
ns
tEHDX
Chip enable high to input transition
0
ns
tWLQZ
(2)(3)
2.
CL = 5pF
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Write enable low to output High-Z
25
ns
tAVWH
Address valid to write enable high
65
ns
tAVEH
Address valid to chip enable high
65
ns
tWHQX
Write enable high to output transition
5
ns
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