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參數(shù)資料
| 型號： | M48T212A-85MH6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | HATLESS, PLASTIC, SOIC-44 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 155K |
| 代理商： | M48T212A-85MH6 |
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M48T212A
24/30
Battery Low Warning
The M48T212A automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0h, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The battery should be
replaced with VCC powering the device to avoid
data loss.
The M48T212A only monitors the battery when a
nominal Vcc is applied to the device. Thus applica-
tions which require extensive durations in the bat-
tery
back-up
mode
should
be
powered-up
periodically (at least once every few months) in or-
der for this technique to be beneficial.
Additionally, if a battery low is indicated, data in-
tegrity should be verified upon power-up via a
checksum or other technique.
Note: Battery Low warning is only valid when us-
ing a 3V button cell battery. Use a super capacitor
for back-up supply causes the BL Flag to be in-
valid.
Initial Power-on Defaults
Upon application of power to the device, the fol-
lowing register bits are set to a ‘0’ state: WDS,
BMB0-BMB4, RB0-RB1, AFE, ABE, W, and FT
(see Table 16).
Table 16. Default Values
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to ’1’ prior to power-down.
Conditi on
W
R
FT
AFE
ABE
WATCHDOG
Register(1)
Initial Power-up (Battery Attach)(2)
010
00
0
RESET(3)
000
00
0
Power-down(4)
010
11
0
Subsequent Power-up
0
1
0
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