參數(shù)資料
型號(hào)： M48T18-150PC1
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDIP28
封裝： 0.600 INCH, ROHS COMPLIANT, PLASTIC, PCDIP-28
文件頁數(shù)： 30/31頁
文件大小： 256K
代理商： M48T18-150PC1
Operation modes
M48T08, M48T08Y, M48T18
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
battery backup switchover voltage (VSO), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Note:
X = VIH or VIL ; VSO = Battery backup switchover voltage.
2.1
Read mode
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip
enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple-
through access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the data I/O pins within address access
time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and G access times are not met, valid data will
Mode
VCC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
VIH
X
High Z
Standby
Deselect
X
VIL
X
High Z
Standby
WRITE
VIL
VIH
XVIL
DIN
Active
READ
VIL
VIH
VIL
VIH
DOUT
Active
READ
VIL
VIH
High Z
Active
Deselect
VSO to
VPFD(min)
(1)
1.
See Table 11 on page 22 for details.
XXX
X
High Z
CMOS standby
Deselect
≤ VSO(1)
X
High Z
Battery backup mode
相關(guān)PDF資料
PDF描述
M48T08-100PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T08-150PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T18-100PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T201V-85MH1TR 1 TIMER(S), REAL TIME CLOCK, PDSO44
M48T201Y-70MH1F 1 TIMER(S), REAL TIME CLOCK, PDSO44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M48T18-150PC1E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
M48T18-150PC1F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
M48T18-150PC1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 8K x 8 TIMEKEEPER SRAM
M48T18MH 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
M48T18PC 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
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