參數(shù)資料
型號(hào)： M48T18-100MH1TR
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： SNAPHAT, PLASTIC, SO-28
文件頁數(shù)： 7/29頁
文件大?。?/td> 184K
代理商： M48T18-100MH1TR
15/29
M48T08, M48T18
Data Retention Mode
With valid VCC applied, the M48T08/18 operates
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T08/18 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T08/18 for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected and the power supply is switched to exter-
nal VCC.
Write protection continues until VCC reaches VPFD
(min) plus tREC (min). E1 should be kept high or E2
low as VCC rises past VPFD (min) to prevent inad-
vertent WRITE cycles prior to system stabilization.
Normal RAM operation can resume tREC after VCC
exceeds VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
Power-fail Interrupt Pin
The M48T08/18 continuously monitors VCC. When
VCC falls to the power-fail detect trip point, an in-
terrupt is immediately generated. An internal clock
provides a delay of between 10s and 40s before
automatically deselecting the M48T08/18. The
INT pin is an open drain output and requires an ex-
ternal pull up resistor, even if the interrupt output
function is not being used.
Figure 11. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD (min).
Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin.
Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
AI00566
VCC
INPUTS
INT
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tPFX
tR
tPFH
tREC
tPD
tRB
tDR
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
相關(guān)PDF資料
PDF描述
M48T18-100MH1 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T18-150PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T08-100PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T08-150PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T18-100PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M48T18-100PC1 功能描述:實(shí)時(shí)時(shí)鐘 64K (8Kx8) 100ns RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
M48T18-100PC1 制造商:STMicroelectronics 功能描述:SRAM TIMEKEEPER 64K 48T18 DIP28
M48T18-100PC1E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
M48T18-100PC1F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
M48T18-100PC1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 8K x 8 TIMEKEEPER SRAM
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