參數(shù)資料
型號(hào): M48T08Y-10PC1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDMA28
封裝: CAPHAT, PLASTIC, DIP-28
文件頁(yè)數(shù): 26/26頁(yè)
文件大?。?/td> 173K
代理商: M48T08Y-10PC1
9/26
M48T08, M48T18, M48T08Y
READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (tAVQV) after the last address input
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
times (tE1LQV or tE2HQV) or Output Enable Access
time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the address
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next address access.
Figure 8. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
AI00962
tAVAV
tAVQV
tAXQX
tE1LQV
tE1LQX
tE1HQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E1
G
DQ0-DQ7
tE2HQV
tE2HQX
VALID
tE2LQZ
E2
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M48T08Y-10PC1E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
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M48T08Y-150MH1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM
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