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參數(shù)資料
| 型號(hào)： | M470L3324BT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| 中文描述： | DDR SDRAM的緩沖模塊18 4針緩沖模塊基于512Mb乙芯片 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | M470L3324BT |
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DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Rev. 0.1 June 2005
Preliminary
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
°
C, f=100MHz)
11.0 Input/Output Capacitance
Parameter
Symbol
M470L3324DU0
Min
41
34
34
25
6
6
M470L6524DU0
Min
49
42
42
25
6
6
M470L2923DV0
Min
65
42
42
28
10
10
Unit
Max
45
38
38
30
7
7
Max
57
50
50
30
7
7
Max
81
50
50
34
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7)
Data & DQS input/output capacitance(DQ0~DQ63)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
pF
pF
pF
pF
pF
pF
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Max
Unit
V
V
V
V
Note
3
3
1
2
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VREF + 0.31
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
10.0 AC Operating Conditions
相關(guān)PDF資料 |
PDF描述 |
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| M470L6524DU0-LB0 | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant) |
| M470L6524DU0-LB3 | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant) |
| M470L6524DU0-LCC | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant) |
| M470L2923DV0-CA2 | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant) |
| M470L2923DV0-CB0 | DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M470L3324BT0-CA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L3324BT0-CB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L3324BT0-CB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L3324BT0-CCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
| M470L3324BT0-CLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb B-die |
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