參數(shù)資料
型號: M464S0924DTS-L7A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
中文描述: 8Mx64 SDRAM內(nèi)存的SODIMM在8M × 16位,4Banks,4K的刷新,3.3V的同步DRAM的社民黨
文件頁數(shù): 10/11頁
文件大?。?/td> 85K
代理商: M464S0924DTS-L7A
M464S0924DTS
PC133/PC100 SODIMM
Rev. 0.1 Sept. 2001
M464S0924DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1H
Organization : 8Mx64
Composition : 8Mx16 * 4
Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L
# of rows in module : 1 Row
# of banks in component : 4 banks
Feature : 1,000mil height & double sided component
Refresh : 4K/64ms
Contents ;
Byte #
Function Described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
9
09h
1
5
# of module
Rows
on this assembly
1
row
01h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time @CAS latency of 3
7.5ns
7.5ns
10ns
10ns
75h
75h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
5.4ns
6ns
6ns
54h
54h
60h
60h
2
11
DIMM configuraion type
Non parity
00h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x16
10h
14
Error checking SDRAM width
None
00h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of
banks
on SDRAM device
4
banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
2 & 3
2 & 3
2 & 3
06h
06h
06h
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
10ns
12ns
75h
A0h
A0h
C0h
2
24
SDRAM access time from clock @CAS latency of 2
5.4ns
6ns
6ns
7ns
54h
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
-
-
00h
00h
00h
00h
26
SDRAM access time from clock @CAS latency of 1
-
-
-
-
00h
00h
00h
00h
27
Minimum row precharge time (=t
RP
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
28
Minimum row active to row active delay (t
RRD
)
15ns
15ns
20ns
20ns
0Fh
0Fh
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
30
Minimum activate precharge time (=t
RAS
)
45ns
45ns
50ns
50ns
2Dh
2Dh
32h
32h
31
Module
Row
density
1
row
of 64MB
10h
32
Command and address signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
33
Command and address signal input hold time
0.8ns
0.8ns
1ns
1ns
08h
08h
10h
10h
34
Data signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M464S0924DTS-L7C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
M464S0924ETS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64MB, 128MB Unbuffered SODIMM
M464S0924ETS-C7A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64MB, 128MB Unbuffered SODIMM
M464S0924ETS-CL7A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64MB, 128MB Unbuffered SODIMM
M464S0924FTS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:144pin Unbuffered SODIMM based on 128Mb F-die 64-bit Non ECC