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參數(shù)資料
| 型號： | M464S0924DTS-L1H |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| 中文描述： | 8Mx64 SDRAM內(nèi)存的SODIMM在8M × 16位，4Banks，4K的刷新，3.3V的同步DRAM的社民黨 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 85K |
| 代理商： | M464S0924DTS-L1H |
M464S0924DTS
PC133/PC100 SODIMM
Rev. 0.1 Sept. 2001
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Sym-
bol
Test Condition
Version
Unit
Note
-7C
-7A
-1H
-1L
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
440
400
400
400
mA
1
Precharge standby current
in power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 10ns
8
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
8
Precharge standby current
in non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
80
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
40
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
20
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
20
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
120
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
100
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks activated
t
CCD
= 2CLKs
560
560
520
520
mA
1
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
880
800
760
760
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
C
8
mA
L
3.2
mA
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
)
Notes :
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M464S0924ETS-C7A | 64MB, 128MB Unbuffered SODIMM |
| M464S0924ETS-CL7A | 64MB, 128MB Unbuffered SODIMM |
| M464S0924DTS-L1L | 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| M464S0924DTS-L7A | 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| M464S0924DTS-L7C | 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M464S0924DTS-L1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| M464S0924DTS-L7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| M464S0924DTS-L7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
| M464S0924ETS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64MB, 128MB Unbuffered SODIMM |
| M464S0924ETS-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64MB, 128MB Unbuffered SODIMM |
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