參數(shù)資料
型號: M41T94MQ6E
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO16
封裝: ROHS COMPLIANT, PLASTIC, SOIC-16
文件頁數(shù): 19/41頁
文件大?。?/td> 352K
代理商: M41T94MQ6E
Clock operations
M41T94
4.10
Output driver pin
When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes
an output driver that reflects the contents of D7 of the control register. In other words, when
D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will
be driven low.
Note:
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
4.11
Battery low warning
The M41T94 automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied. In order to insure data integrity during subsequent periods of
battery backup mode, the battery should be replaced. The SNAPHAT top may be replaced
while VCC is applied to the device.
Note:
This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is
disconnected.
The M41T94 only monitors the battery when a nominal VCC is applied to the device. Thus
applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
4.12
tREC bit
Bit D7 of clock register 04h contains the tREC bit (TR). tREC refers to the automatic
continuation of the deselect time after VCC reaches VPFD. This allows for a voltage setting
time before WRITEs may again be performed to the device after a power-down condition.
The tREC bit will allow the user to set the length of this deselect time as defined by Table 8
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