參數(shù)資料
型號: M41T83SQA6E
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, QCC16
封裝: 4 X 4 MM, ROHS COMPLIANT, QFN-16
文件頁數(shù): 19/61頁
文件大小: 983K
代理商: M41T83SQA6E
Clock operation
M41T82-M41T83
Doc ID 12578 Rev 12
3.4
Clock calibration
The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When
the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at
25 °C.
The M41T8x design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the
100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100 Hz
divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to
provide the input frequency to the fraction of seconds clock register. By adjusting the
number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped
up or slowed down, as shown in Figure 19 on page 32.
When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the
digital calibration register (08h) and the sign bit is 1, (indicating positive calibration), the
100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512.
Since the 100 pulses are now being output in a shorter window, this has the effect of
speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when
the sign bit is 0, indicating negative calibration, the block outputs 100 pulses for every 513
input pulses. Since the 100 pulses are then being output in a longer window, this has the
effect of slowing down the clock by 1/512 seconds for each second the circuit is active.
The amount of calibration is controlled by using the value in the calibration register (N) to
generate the adjustment in one second increments. This is done for the first N seconds once
every eight minutes for positive calibration, and for N seconds once every sixteen minutes
for negative calibration (see Table 6 on page 28).
For example, if the calibration register is set to 100010, then the adjustment will occur for
two seconds in every minute. Similarly, if the calibration register is set to 000011, then the
adjustment will occur for 3 seconds in every alternating minute.
The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital
calibration register (08h). These bits can be set to represent any value between 0 and 31 in
binary form. The sixth bit (DCS) is a sign bit; 1 indicates positive calibration, 0 indicates
negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)
cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034
ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments
in the calibration byte would represent +10.7 or –5.35 seconds per month, which
corresponds to a total range of +5.5 or –2.75 minutes per month.
One method of determining the amount of digital calibration required is to use the frequency
test output (FT) of the device (see Section 3.14: IRQ1/FT/OUT pin, frequency test,
interrupts and the OUT bit (M41T83 only) on page 41 for more information on enabling the
FT output).
When FT is enabled, a 512 Hz signal is output in the IRQ1/FT/OUT pin on the M41T83, and
on the FT/RST pin on the M41T82. This signal can be measured using a highly accurate
timing device such as a frequency counter. The measured value is then compared to 512 Hz
and the oscillator error in ppm is then determined.
The user should keep in mind that changes in the digital calibration value will not affect the
signal measured on the FT pin. While the analog calibration circuit does affect the oscillator,
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