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參數(shù)資料
| 型號： | M41T82SQA6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, QCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, QFN-16 |
| 文件頁數(shù)： | 33/58頁 |
| 文件大?。?/td> | 462K |
| 代理商： | M41T82SQA6F |
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M41T82 M41T83
Clock operation
3.8.2
Timer flag (TF)
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI/TP bit). The TF bit is cleared by reading the Flags Register.
3.8.3
Timer interrupt enable (TIE, M41T83 only)
In Level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To
clear the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
Timer enable (TE)
●
TE = 0
When the Timer Register (10h) is set to ‘0’, the timer is disabled.
●
TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
3.8.5
TD1/0
These are the timer source clock frequency selection bits (see Table 11). These bits
determine the source clock for the countdown timer (see Table 12). When not in use, the
TD1 and TD0 bits should be set to ‘11’ (1/60 Hz) for power saving.
Table 10.
Interrupt operation (bit TI/TP = 1)
Source clock (Hz)
IRQ(1) periods
1.
TF and IRQ1/FT/OUT become active simultaneously.
n(2) = 1
2.
n = loaded countdown timer value. The timer is stopped when n = 0.
n > 1
4096
1/8192
1/4096
64
1/128
1/64
11/64
1/64
1/60
1/64
Table 11.
Timer source clock frequency selection (244.1 s to 4.25 hrs)
TD1
TD0
Timer source clock frequency (Hz)
0
4096 (244.1 s)
0
1
64 (15.6 ms)
10
1 (1 s)
1
1/60 (60 s)
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