M41T82-M41T83
Clock operation
Doc ID 12578 Rev 12
A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but not de-
assert the IRQ1/FT/OUT output. The watchdog function is automatically disabled upon
3.8
8-bit (countdown) timer
The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the
timer control register (11h) TE bit. Other timer properties such as the source clock, or
interrupt generation are also selected in the timer control register (see
Table 10). For
accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a
frequency of at least twice the selected timer clock.
The timer control register selects one of four source clock frequencies for the timer (4096,
64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a software-
loaded 8-bit binary value (register 10h) and decrements to 1. On the next tick of the counter,
it reloads the timer countdown value and sets the timer flag (TF) bit. The TF bit can only be
cleared by software. When asserted, the timer flag (TF) can also be used to generate an
interrupt (IRQ1/FT/OUT) on the M41T83. Writing the timer countdown value (10h) has no
effect on the TF bit or the IRQ1/FT/OUT output.
3.8.1
M41T83 timer interrupt/output
On the M41T83, there are two choices for the output depending on the TI/TP configuration
bit (timer interrupt/timer pulse, bit 6, register 11h).
Normal interrupt mode
With TI/TP = 0, the output will assert like a normal interrupt, staying low until the TF bit is
cleared by software by reading the flags register (0Fh).
Free-running mode
When TI/TP is a 1, the output is a free-running waveform as depicted in
Figure 21. After
being low for the specified time (as shown in
Table 11), the output automatically goes high
without need of software clearing any bits. The TF bit will still be set each time the timer
reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing
the TF bit has no effect on the output in this mode.
While writes to the timer countdown register (10h) control the reload value, reads of this
register return the current countdown timer value.
Table 9.
Watchdog register
Addr
D7
D6
D5
D4
D3
D2
D1
D0
Function
09h
OFIE
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog