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參數(shù)資料
| 型號： | M41T82RMY6E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO18 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-18 |
| 文件頁數(shù)： | 29/58頁 |
| 文件大小： | 462K |
| 代理商： | M41T82RMY6E |
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M41T82 M41T83
Clock operation
Figure 20.
Crystal isolation example
1.
Substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Address locations 0Ah-0Eh (Alarm 1) and 14h-18h (Alarm 2) contain the alarm settings.
Either alarm can be configured independently to go off at a prescribed time on a specific
month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or
second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of
operation. Table8 on page37 shows the possible bit configurations.
Codes not listed in the table default to the once-per-second mode to quickly alert the user of
an incorrect alarm setting. When the clock information matches the alarm clock settings
based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (Alarm 1
Flag) or AF2 (Alarm 2 Flag) is set. If A1IE (Alarm 1 Interrupt Enable), or A2IE (Alarm 2
Interrupt Enable) are also set, the alarm condition activates either the IRQ1/FT/OUT, or
IRQ2 output pins. To disable either of the alarms, write a '0' to the Alarm Date Registers and
to the RPTx5–RPTx1 bits.
Note:
If the address pointer is allowed to increment to the Flag Register address, or the last
address written is “Alarm Seconds,” the address pointer will increment to the Flag address,
and an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is
moved to a different address.
The IRQ output is cleared by a READ to the Flags Register (0Fh) as shown in Figure 21. A
subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag
has been reset to '0'.
AI11814
Crystal
XI XO
VSS
Local Grounding
Plane (Layer 2)
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