參數(shù)資料
型號: M41T81MQ6TR
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO16
封裝: PLASTIC, SOIC-16
文件頁數(shù): 4/28頁
文件大小: 179K
代理商: M41T81MQ6TR
M41T81
12/28
Read Mode
In this mode the master reads the M41T81 slave
after setting the slave address (see Figure 11,
page 13). Following the write mode control bit (R/
W=0) and the acknowledge bit, the word address
‘An’ is written to the on-chip address pointer. Next
the START condition and slave address are re-
peated followed by the READ mode control bit (R/
W=1).
At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an acknowledge bit to the slave
transmitter.
The address pointer is only incre-
mented on reception of an acknowledge bit. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a RAM address.
An alternate READ mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 12, page 13).
Write Mode
In this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 13, page 13. Following the START con-
dition and slave address, a logic ‘0’ (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer.
The
data word to be written to the memory is strobed in
next and the internal address pointer is increment-
ed to the next memory location within the RAM on
the reception of an acknowledge clock.
The
M41T81 slave receiver will send an acknowledge
clock to the master transmitter after it has received
the slave address (see Figure 8, page 10) and
again after it has received the word address and
each data byte.
Figure 10. Slave Address Location
AI00602
R/W
SLAVE ADDRESS
START
A
0
100
0
11
MSB
LSB
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